Semiconductor integrated circuits (IC) typically include metallization layers used to connect various components of the IC, called interconnect, or back end of line (BEOL). Copper may be preferred over aluminum due to its lower resistivity and high electro-migration resistance. Copper interconnect, however, is difficult to manufacture with traditional photoresist masking and plasma etching used for aluminum interconnect.
One known technique for forming copper interconnects on an IC is known as additive patterning, sometimes called a Damascene process, which refers to traditional metal inlaying techniques. A so-called Damascene process may include patterning dielectric materials, such as silicon dioxide, or fluorosilicate glass (FSG), or organo-silicate glass (OSG) with open trenches where the copper or other metal conductors should be. A Copper diffusion barrier layer (typically Ta, TaN, or bi-layer of both) is deposited, followed by a deposited Copper seed layer. It is usually followed by the bulk Copper fill, typically through Electro-Chemical Plating process. Chemical-mechanical planarization (CMP) process is then used to remove any excessive copper and barrier. This CMP process is typically referred as Copper CMP process. The copper remaining in the trench then functions as a conductor. Typically, the wafer is immediately deposited with a dielectric barrier layer, such as SiN or SiC to prevent Copper corrosion and improve device reliability.
With more features packed into a semiconductor chip, there is more need to pack passive components, such as resistors, into the circuits. Some resistors can be created through ion implantation and diffusion, such as poly resistors. However, such resistors have high variations in its resistance value, and also its resistance value changes drastically with temperature.